Senior ASIC RTL Design Engineer, AI Networking IP
Core
Design high-performance networking and communications IP cores for advanced AMD products using ASIC RTL design.
Role type
Senior IC ASIC RTL Design Engineer
Builds
IP cores for networking, security, storage, and AI applications
Domain
Semiconductor / AI Networking / ASIC Design
Deliverable
production ML models
Required skills
Verilog/SystemVerilog, ASIC front-end design flows, high-speed interface protocols (Ethernet, PCIe, AXI), synthesis and timing closure, functional verification tools (Synopsys, Cadence, Siemens), scripting (Python, Perl, TCL, Bash), AI tools for code generation
Preferred skills
AI-powered RTL design tools (VS Code, GitHub Copilot, Cursor), LLM integration (Claude, Codex/GPT), emulation support, encryption protocols (MACsec, IPsec), optical communications, packet processing
Technologies
Verilog, SystemVerilog, Synopsys, Cadence, Siemens, VS Code, GitHub Copilot, Cursor, Python, Perl, TCL, Bash, AXI, AHB, AMBA, Ethernet, PCIe, MACsec, IPsec
Responsibilities
Develop synthesizable RTL for IP cores targeting advanced technology nodes, Utilize modern AI tools to achieve a high level of RTL design productivity through code generation, refactoring, documentation, and debug, Collaborate directly with IP Architecture, IP Verification, and SoC integration teams, Contribute to design specifications for IP cores, Resolve IP simulation regression failures through close collaboration with the IP Verification Team, Work with the SoC and Physical Design (PD) teams to meet Power/Performance/Area goals by providing synthesis and timing closure support, Coach and mentor less experienced designers
Seniority
Senior, hands-on IC
