Standard Cell Design Enablement Lead
Core
Developing and managing standard cell libraries for AMD products, ensuring they meet performance, power, area, and cost requirements in advanced CMOS technologies.
Role type
Standard Cell Design Enablement Lead
Builds
Standard cell libraries for AMD processors and AI technologies
Domain
Semiconductor / Integrated Circuit Design
Required skills
Semiconductor device physics, fabrication processes, EDA tools (Synopsys/CDNS/Siemens), PDK, DRC, LVS, Virtuoso, PEX, capacitance modeling, EMIR, reliability analysis, IR Drop analysis, SPICE simulation, Unix shell, Perl, Python
Preferred skills
Standard cell design and layout analysis, Schematic and layout entry, physical and logical verification, extraction, timing characterization, scripting
Technologies
Synopsys, Cadence, Siemens, Virtuoso, Perl, Python, Unix
Responsibilities
Coordinate with external standard cell library vendors on schedules and requirements, oversee download, build, release, and QA of libraries, address requests and issues for standard cells
Seniority
Senior, hands-on IC
