Lead DFT Engineer
Core
Lead DFT Engineer responsible for implementing and verifying digital design for test (DFT) features, ATPG patterns, and post-silicon support to ensure yield and bring-up.
Role type
Senior IC DFT Engineer
Builds
High-quality, industry-leading semiconductor processors and chips
Domain
Semiconductor / Digital IC Design
Required skills
DFT implementation, Scan insertion, ATPG pattern generation, MBIST/BISR implementation, Spyglass-DFTDRC debug, Gate-level simulation, Test coverage analysis, JTAG basics, Debug skills, Scripting (TCL/AWK/SED)
Preferred skills
Scan-stitching concepts, Tessent flow (MBIST), Tessent ATPG (Mentor), Post-silicon bring-up experience
Technologies
Spyglass-DFT, Tessent, Mentor ATPG, TCL, AWK, SED
Responsibilities
Implement and verify DFT features (SCAN, MBIST, LBIST, JTAG), Support Spyglass-DFTDRC debug and coverage correlation, Perform scan insertion and ATPG pattern generation, Verify ATPG patterns with gate-level simulation, Analyze test coverage and test cost reduction, Provide post-silicon support for bring-up and yield learning
Seniority
Senior, hands-on IC
