Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Core
Design and optimization of hardware for cloud server platforms, specifically focusing on Static Timing Analysis (STA) for products like AWS Inferentia.
Role type
Senior IC physical design engineer (static timing analysis)
Builds
High-performance, low-cost machine learning inference chips for AWS data centers
Domain
Semiconductor hardware design / Cloud infrastructure
Deliverable
production ML models
Required skills
Static Timing Analysis fundamentals, timing constraint development, EDA tools (PrimeTime, Tempus), ASIC Physical Design (RTL-to-GDSII), scripting (Python, Ruby, Perl), sign-off activities (IR/EM, physical verification, DFT)
Preferred skills
Mentoring and coaching, advanced node experience (16nm or below), parasitic extraction tools (STAR-RC, Quantus), circuit level analysis (SPICE, SPECTRE), IO interface timing (DDR, HBM, PCIe, Die-to-Die)
Technologies
PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker, STAR-RC, Quantus, SPICE, SPECTRE
Responsibilities
Develop and maintain flows for block and full-chip level static timing analysis, write and debug timing constraints, run STA and provide feedback, guide fixes for timing issues (ECOs, constraint fixes), develop automation scripts for timing analysis and reporting
Seniority
Senior, hands-on IC