ASIC Physical Design & Implementation Lead
Core
Lead physical design for next-generation ASICs, managing the flow from RTL to GDS2 to meet engineering, business, and customer requirements.
Role type
Senior IC ASIC Physical Design Lead
Builds
Next-generation ASIC chips for high-performance applications
Domain
Semiconductor / Hardware Design
Required skills
RTL to GDS2 flow implementation, Floor planning, Power planning, Synthesis, Placement, CTS, Timing closure, Routing, DRC/LVS verification, EM/IR analysis, Formal equivalence, Scripting for flow automation, FinFET node expertise (5nm-16nm), High-speed datapath design
Preferred skills
Automated synthesis and timing-driven place-and-route, IP integration, Design optimization for timing/power/area, Computer organization/architecture knowledge, Geographically distributed team collaboration
Technologies
Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
Responsibilities
Implement RTL to GDS2 flow, Handle full chip level floor planning, bus/pin planning, and clock tree synthesis, Drive hands-on flow development and scripting, Identify and solve complex technical problems, Perform physical verification and sign-off
Seniority
Senior, hands-on IC
