Lead DFT Engineer
Core
Lead DFT Engineer responsible for developing test strategies, generating test vectors, and verifying DFT patterns to ensure First-Time-Right (FTR) quality for AMD's next-gen processors.
Role type
Senior IC Design for Test (DFT) Engineer
Builds
Test vectors and DFT patterns for silicon-equivalent environments
Domain
Semiconductor / Digital Design / Test Engineering
Required skills
ATPG (Automatic Test Pattern Generation), Scan-stitching, Test vector generation, Non-scan DFT pattern verification, Post-silicon engineering collaboration, Electronics/Electrical Engineering fundamentals
Preferred skills
Tessent ATPG (Mentor), Post-silicon bring-up experience
Technologies
Tessent ATPG, VTPx, DVT
Responsibilities
Prepare and deliver test vectors based on design/architecture; Verify non-scan DFT patterns in silicon-equivalent environments; Collaborate with post-silicon engineering teams; Execute scan-stitching concepts and ATPG runs
Seniority
Senior, hands-on IC
