Static Timing Analysis / Full Chip Timing Engineer
Core
Own full-chip static timing analysis (STA) and timing closure for complex SoC designs from early netlist through final signoff.
Role type
Senior IC static timing analysis engineer
Builds
Complex System-on-Chip (SoC) designs
Domain
Semiconductor / Digital IC Design
Required skills
Full-chip STA, Multi-corner/multi-mode (MMMC) timing convergence, Setup/Hold/DRV signoff, SI/crosstalk analysis, Clock tree synthesis (CTS) strategy, ECO generation, SDC constraint analysis, Root-cause analysis, Flow automation, PnR collaboration
Preferred skills
Full chip timing experience
Technologies
STA tools, PnR tools, SDC, CTS methodologies (H-tree, MSCTS, clock mesh)
Responsibilities
Drive multi-corner/multi-mode timing convergence across PVT corners; Analyze and resolve SI/crosstalk, OCV/POCV, and clock-related impacts; Perform root-cause analysis of timing violations and drive fixes through ECOs; Guide clock tree build strategy and define skew/latency targets; Collaborate with PnR and synthesis teams for timing convergence; Build automation for design signoff checks and QoR tracking.
Seniority
Senior, hands-on IC
