Staff Physical Design Engineer
Core
Back End Physical Design engineer responsible for floor-planning, power planning, synthesis, placement, CTS, timing closure, routing, extraction, and physical verification (DRC & LVS) for high-performance processors.
Role type
Staff Physical Design Engineer (IC)
Builds
Next-generation processors and industry-leading technologies
Domain
Semiconductor / Digital IC Design
Required skills
Floor-planning, Power planning, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, DRC, LVS, Crosstalk Analysis, EM/IR, Tcl scripting, Perl scripting, Python scripting
Preferred skills
FinFET & Dual Patterning nodes experience, High-frequency design, RTL exposure, MNC experience
Technologies
Synopsys Design Compiler, ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
Responsibilities
Execute floor-plan, physical implementation of power-plan, synthesis, placement, CTS, timing closure, routing, extraction, and physical verification; Author methodology scripts in Tcl, Perl, and Python; Collaborate with engineers across different sites and timezones
Seniority
Staff, hands-on IC
