Memory PHY Principal Design Engineer
Core
Architect and develop high-speed memory interface IP (LPDDR, DDR) including digital PHY architecture, RTL, and firmware.
Role type
Principal IC design engineer (Memory PHY)
Builds
High-speed memory interface IP for processors
Domain
Semiconductor / Memory Interface
Required skills
Memory PHY architecture, Verilog/SystemVerilog, digital design methodologies, Python/Perl/Tcl scripting, mixed-signal integration, clocking architectures, low-power design, synthesis, static timing analysis, timing closure, silicon bring-up
Preferred skills
Power-management microarchitecture, mentoring engineers, cross-functional leadership
Technologies
LPDDR, DDR, GDDR, HBM, SerDes, UPF
Responsibilities
Define product features and technical specifications, lead digital architecture development from pathfinding to physical realization, architect PHY link-layer functionality, drive analog and digital co-design, guide synthesis and timing closure, collaborate with verification and firmware teams, identify technical risks and drive solutions, support post-silicon debugging, advance AI-assisted design methodologies
Seniority
Principal, hands-on IC with mentorship
