FCT PD lead
Core
Developing, validating, and maintaining timing constraints (SDC) and driving full-chip timing convergence for complex System-on-Chip (SoC) designs.
Role type
Senior IC silicon design engineer (full-chip timing)
Builds
Next-generation processors (CPU, GPU, AI/ML, networking) and complex SoCs
Domain
Semiconductor / VLSI / Physical Design
Required skills
Static Timing Analysis (STA), SDC constraint development, Synopsys PrimeTime, clocking architecture, CDC analysis, Tcl/Python/Perl scripting, timing signoff methodologies
Preferred skills
Full-chip timing closure for large SoCs, constraint quality checks, low-power timing (UPF), advanced-node tapeout support (5nm/4nm/3nm), timing automation development
Technologies
Synopsys PrimeTime, PrimeTime-SI, Tempus, Fusion Compiler, Tcl, Python, Perl, Shell
Responsibilities
Develop and validate block, subsystem, and SoC-level timing constraints; Perform comprehensive timing analysis and closure for full-chip designs; Debug timing violations across RTL, clocking, and physical implementation; Drive timing convergence across multiple corners and modes; Develop timing automation and QoR dashboards; Mentor junior engineers on timing methodologies
Seniority
Senior, hands-on IC
