PTPX Power/PNR Engineer
Core
Power analysis, optimization, and signoff of complex SoC/IP designs using PrimeTime PX (PTPX) to drive dynamic and leakage power convergence.
Role type
Senior IC physical design engineer (power analysis)
Builds
Next-gen processors (CPU, GPU, AI/ML, networking, datacenter)
Domain
Semiconductor / VLSI / ASIC Physical Design
Required skills
PrimeTime PX (PTPX), ASIC Physical Design, Static Timing Analysis (STA), CMOS power fundamentals, low-power design techniques, SAIF/VCD-based power analysis, scripting (Tcl, Python, Perl, Shell), debugging, correlation of RTL/synthesis/implementation/silicon power
Preferred skills
SoC power signoff for CPU/GPU/AI/ML/networking/datacenter, clock power optimization, power gating, multi-Vt strategies, DVFS, advanced process nodes (5nm/4nm/3nm), RedHawk/Joules/PowerArtist, UPF/CPF, IR/EM, thermal-aware power analysis, mentoring
Technologies
PrimeTime PX, Fusion Compiler, RedHawk, Joules, PowerArtist, Tcl, Python, Perl, Shell, SAIF, VCD, UPF, CPF
Responsibilities
Perform block, tile, and full-chip power analysis; Analyze dynamic, leakage, clock, memory, and switching power components; Drive power convergence across project milestones; Correlate power across RTL, synthesis, implementation, and silicon projections; Debug high-power hotspots and recommend optimizations; Execute power regression flows and generate dashboards/reports; Collaborate with PD, timing, clocking, and RTL teams; Develop automation scripts and methodologies
Seniority
Senior, hands-on IC
