PD Clocking Engineer
Core
Own and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs, developing implementation flows and automation frameworks.
Role type
Senior IC Physical Design Methodology Engineer
Builds
ASIC/SoC physical design implementations and verification flows
Domain
Semiconductor / VLSI Physical Design
Required skills
Clock-tree synthesis, timing closure, PnR flow development, Tcl scripting, Python scripting, Shell scripting, EDA tool expertise, cross-functional collaboration
Preferred skills
Advanced technology node experience (5nm/3nm), flow ownership, methodology certification
Technologies
Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, RedHawk, Tcl, Python, Shell
Responsibilities
Own end-to-end clocking methodology including CTS architecture and skew management; Develop and maintain PnR implementation flows; Drive flow correlation between Tile PnR, FCT, STA, and signoff environments; Define implementation recipes for timing, congestion, power, and area closure; Develop automation scripts to improve productivity and flow robustness; Partner with CAD, Timing, and Design teams to resolve methodology issues; Enable new technology nodes and validate EDA tool features.
