DFT/DFx Architecture & RTL Lead
Core
Lead DFT/DFx architecture definition, RTL implementation, and methodology development for high-speed SerDes, Memory PHY, and die-to-die interconnect IPs.
Role type
Senior IC DFT/DFx Architecture & RTL Lead
Builds
Advanced PHY and connectivity IP designs for SoCs
Domain
Semiconductor / Digital Design / Test Engineering
Required skills
DFT/DFx architecture, RTL coding (Verilog/SystemVerilog), scan integration, ATPG support, MBIST planning, gate-level simulation, test constraints, silicon debug, low-power design concepts, fault models
Preferred skills
Siemens Tessent flows, hierarchical DFT, JTAG/IJTAG, scan compression, lint/DFT-readiness analysis, cross-functional collaboration
Technologies
Verilog, SystemVerilog, Synopsys VCS, Verdi, SpyGlass, Siemens Tessent, Synopsys Design Compiler, Cadence Innovus
Responsibilities
Define PHY-specific DFT/DFx architecture and methodology, implement DFT features in RTL, support ATPG and scan integration, develop MBIST features, perform gate-level simulation and debug, drive lint/DFT-readiness analysis, partner on silicon bring-up and yield learning
Seniority
Senior, hands-on IC
