Lead Design Verification Engineer-Memory Controller
Core
Architecting and leading verification strategies for cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC) to ensure first-pass silicon success.
Role type
Senior Staff Silicon Design Verification Engineer (Memory Controller & SoC)
Builds
Pre-Silicon Design IP and SoC designs for high-performance computing and AI
Domain
Semiconductor / VLSI Design / Memory Controllers
Required skills
UVM, System Verilog, Formal Verification, Assertion-Based Verification, Memory Controller Protocols (DDR/LPDDR/HBM), Verification Planning & Strategy, Team Leadership, Regression Management
Preferred skills
Board skew and jitter modeling, Gate-level simulation, Power-aware verification, Silicon debug, Verification management tools
Technologies
Synopsys VCS, Cadence Xcelium, VC Formal, JasperGold, Questa Formal
Responsibilities
Lead verification of high-speed Crypto, NoC, and DRAM Memory controller designs; Architect and develop simulation/formal verification environments at IP and SoC-level; Lead and manage verification teams including planning and closure; Develop comprehensive verification plans and testbenches; Collaborate with design and architecture teams; Mentor junior engineers
Seniority
Senior Staff, hands-on IC with leadership
