Interconnect Micro-architect/RTL Design Engineer
Core
Design next-generation coherent interconnects (Infinity Fabric) connecting CPU, GPU, and accelerators for AMD products.
Role type
Senior IC RTL Design Engineer (Micro-architecture)
Builds
Custom-designed Infinity Data Fabric for servers, HPC, PCs, AI, graphics, and gaming
Domain
Semiconductor / High-performance computing / Processor architecture
Required skills
Verilog, System Verilog, Micro-architecture definition, Power/Performance/Area/Timing optimization, Assertion creation, Post-silicon debug, Digital electronics, High-speed design (>1GHz), Multi-processor coherency, Cache design, DFT/Scan concepts
Preferred skills
CPU/GPU/NOC/Cache design experience, C/C++/Python, x86 or ARM ISA knowledge
Technologies
Verilog, System Verilog, C, C++, Perl, Python, x86, ARM
Responsibilities
Define micro-architecture and design logic blocks; Optimize designs for PPA and timing; Write synthesizable RTL; Create assertions and unit tests; Write block-level documentation; Participate in post-silicon debug and tuning.
Seniority
Senior, hands-on IC
