Staff/Principal Functional Verification Engineer (Memory Subsystem)
Core
Provide technical leadership and develop simulation/formal verification environments to prove functional correctness of UCIe, DDR5/6, and HBM memory controller designs.
Role type
Staff/Principal Functional Verification Engineer (Memory Subsystem)
Builds
High-performance memory controller IPs and System-on-Chip (SoC) designs
Domain
Semiconductor / High-speed memory interfaces
Required skills
UVM/OVM, System Verilog, Verilog, Synopsys VCS, Cadence IES, memory controller protocols, skew and jitter modeling, technical leadership, verification strategy, assertion-based verification, metric-driven verification, regression management, formal property checking, gate-level simulation, power verification, silicon debug
Preferred skills
UCIe verification, verification architecture, verification methodology establishment, formal property checking tools (Jasper, Synopsys), gate-level simulation, power verification, reset verification, contention checking, board-level silicon debug
Technologies
UCIe, DDR5, DDR6, HBM, LPDDR, Synopsys VCS, Cadence IES, Jasper, System Verilog, UVM, OVM
Responsibilities
Design and develop simulation and formal verification environments at block and system levels, drive verification strategies for high-performance IPs, lead teams of 9+ engineers in planning and execution, influence design teams to improve product quality, manage verification closure and delivery
Seniority
Staff/Principal, hands-on IC with technical leadership
