Lead Physical Design Engineer, Place & Route
Core
Lead physical implementation activities for complex AI and high-performance computing designs, driving place-and-route execution from floorplanning through signoff.
Role type
Senior hands-on IC physical design engineer (place & route)
Builds
Leading-edge AI and graphics products on advanced process technologies
Domain
Semiconductor / ASIC physical design
Deliverable
production ML models
Required skills
Place-and-route methodologies, floorplanning, placement, clock tree synthesis, routing, timing closure, congestion closure, power closure, physical verification, signoff (ERC/LVS), EDA tools (Synopsys Fusion Compiler, Cadence, Siemens), scripting (TCL/Perl/Shell), technical leadership
Preferred skills
ASIC physical design flows, advanced-node implementation, high-speed design, technical direction across complex projects
Technologies
Synopsys Fusion Compiler, Cadence, Siemens EDA tools, TCL, Perl, Shell
Responsibilities
Lead place-and-route execution from floorplanning through signoff; Drive timing, congestion, and power closure; Develop and optimize floorplanning, placement, clock tree, and routing strategies; Identify and resolve critical physical design issues; Perform timing analysis, parasitic extraction, and power integrity analysis; Execute physical verification and signoff activities; Enhance physical design methodologies and automation flows
Seniority
Senior, hands-on IC
