Memory PHY - Technical Lead
Core
Technical lead responsible for integrating and supporting third-party Memory/Serdes PHY and mixed-signal IP across AMD products, managing the lifecycle from architecture to production.
Role type
Senior IC Technical Lead (Memory PHY & Mixed-Signal IP)
Builds
High-speed memory interfaces (HBM, DDR, LPDDR, GDDR) and SerDes blocks integrated into AMD SoCs
Domain
Semiconductor hardware design, high-speed digital/analog interfaces, SoC integration
Required skills
High-speed mixed-signal IP design, SerDes/Memory PHY architecture, SoC integration, system-level architecture, signal integrity analysis, post-silicon validation, transistor-level design understanding
Preferred skills
FinFET technology (7nm and below), RTL/logic design basics, Python/Perl programming, lab equipment usage (BERT, oscilloscope)
Technologies
HBM, LPDDR, DDR, GDDR, PCIe, Ethernet, USB, DisplayPort, HDMI, MIPI, CTLE, FFE, DFE, VGA, CDR, PLL/DLL
Responsibilities
Provide technical leadership for IP/PHY throughout the product lifecycle; Collaborate with third-party IP vendors for evaluation and integration; Partner with SoC integration teams to ensure quality; Drive system-level architectural decisions; Support package/PCB design with signal integrity analysis; Direct post-silicon bring-up, debug, and characterization; Analyze results to drive future architecture improvements
Seniority
Senior, hands-on IC
