CareerPlan

CPU Core Staff DFT Engineer

Santa Clara, CaliforniaFull-time2026-09-11 → 2026-10-22
No visa sponsorship

Core

Own ATPG/DFT responsibilities for next-generation AMD high-performance cores to ensure first-pass silicon success.

Role type

Senior IC DFT Engineer

Builds

High-performance CPU cores

Domain

Semiconductor / CPU Design

Required skills

ATPG (Stuck-At, At-Speed, Path-Delay), Scan Compression, Verilog, Linux, Perl/TCL scripting, DFT tools, JTAG, MBIST, IEEE 1149.1/1500/1687 standards

Preferred skills

Commercial test generation tools, Tessent Scan/ATPG flows, Silicon bring-up/debug on ATE, 7nm+ process nodes, Agentic AI for flow development

Technologies

Verilog, Perl, TCL, Linux, Tessent, ATE

Responsibilities

Debug low coverage and DRC violations, debug complex test pattern issues and simulation failures, support silicon bring-up activities, participate in post-silicon debug

Seniority

Senior, hands-on IC