Lead Physical Design Engineer
Core
Lead physical design for complex ASIC and SoC products, driving implementation, timing closure, and optimization for next-gen AI and high-performance computing silicon.
Role type
Senior IC physical design engineer
Builds
Next-generation AI and high-performance computing silicon chips
Domain
Semiconductor / Advanced-node ASIC design
Deliverable
production ML models
Required skills
ASIC physical design, timing closure, static timing analysis, clock-tree optimization, ECO strategies, formal verification, scripting (TCL/Python/Perl), data analysis
Preferred skills
Machine learning-driven design optimization, advanced-node process technologies, design flow development
Technologies
Synopsys ICC2, Fusion Compiler, Cadence Innovus, PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, Conformal, Pandas
Responsibilities
Lead physical design activities across block, subsystem, and chip-level implementations; Drive timing closure, signoff readiness, and PPA optimization; Develop and enhance physical design methodologies and automation solutions; Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization; Define and execute engineering change (ECO) strategies; Support formal verification, physical verification, and tapeout preparation; Analyze design data and trends to improve quality and efficiency; Collaborate with cross-functional teams for silicon delivery; Troubleshoot complex implementation challenges.
Seniority
Senior, hands-on IC
