ASIC Physical Design & Implementation Lead
Core
Lead physical design for next-generation ASICs, driving floorplanning, implementation, and sign-off to meet Power Performance Area (PPA) targets for AECG customers.
Role type
Senior IC ASIC Physical Design Lead
Builds
Next-generation ASICs for AECG customers
Domain
Semiconductor / ASIC Physical Design
Required skills
RTL to GDS2 flow implementation, floorplanning, clock tree synthesis, placement, routing, timing closure, physical verification (DRC/LVS), EM/IR analysis, formal equivalence checking, scripting for flow automation, FinFET node expertise (5nm-16nm), high-performance design optimization
Preferred skills
Automated synthesis and timing-driven place-and-route, IP integration, design methodology establishment, computer organization/architecture knowledge, cross-functional collaboration
Technologies
Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
Responsibilities
Drive RTL to GDS2 flow from floorplanning to sign-off, handle full-chip level tasks including bus/pin planning and static timing analysis, identify and solve complex technical problems, develop and optimize design flows using scripting
Seniority
Senior, hands-on IC
