Fullchip Floorplan Physical Design Engineer
Core
Full-chip floorplanning, physical implementation, timing closure, and power optimization for complex SoC designs.
Role type
Senior IC physical design engineer (floorplanning & implementation)
Builds
High-performance, power-efficient silicon solutions (processors/SoCs)
Domain
Semiconductor / SoC Physical Design
Required skills
full-chip floorplanning, synthesis, place and route, timing closure, power optimization, EDA tool usage (Cadence Innovus, Synopsys ICC, Calibre), automation scripting (Tcl, Perl, Python), low-power design techniques, macro integration, block placement strategy
Preferred skills
SoC implementation and tapeout experience, Synopsys Fusion Compiler (FC), SoC architecture knowledge (AXI buses, source synchronous design), Verilog RTL design, Perl and Shell scripting
Technologies
Cadence Innovus, Synopsys ICC, Calibre, Synopsys Fusion Compiler, Tcl, Perl, Python, Verilog
Responsibilities
Define chip-level partitioning, block placement strategy, and macro integration; Optimize full-chip floorplan for timing, power, and area; Develop and maintain automation scripts for floorplanning efficiency; Conduct layout feasibility studies through what-if analysis; Apply low-power design techniques and voltage domain crossing checks
Seniority
Senior, hands-on IC
