CareerPlan

2027 Masters ASIC Package Engineering Co-op/Intern

Santa Clara, California; San Jose, CaliforniaInternship2026-08-25 → 2026-11-10
HybridNo visa sponsorship

Core

Support Package design and Package Development Engineers in prioritizing and optimizing new projects for advanced packaging technology.

Role type

Masters level ASIC Package Engineering Co-op/Intern

Builds

Substrate, interposer, and bump designs for AMD products, test vehicles, and probe card substrates

Domain

Semiconductor manufacturing and advanced packaging

Required skills

Package design, substrate design, interposer design, bump design, design verification, yield analysis, defect analysis, material benchmarking, Perl, Python, SQL, PowerBI

Preferred skills

Transmission lines and electric circuits, PCB design software, semiconductor theory, packaging process/technology

Technologies

Perl, Python, SQL, PowerBI

Responsibilities

Support package design and development engineers in project prioritization and optimization; Complete substrate, interposer, and bump designs; Execute design verification implementation projects; Analyze yield and defect metrics to improve design performance; Evaluate and benchmark packaging materials for cost efficiency and performance.

Seniority

Masters student, hands-on IC