CareerPlan

2027 Undergrad ASIC Package Engineering Co-op/Intern

San Jose, California; Santa Clara, CaliforniaInternship2026-08-25 → 2026-11-10
Hybrid · United StatesNo visa sponsorship

Core

Support Package design and Package Development Engineers in prioritizing and optimizing new projects for advanced packaging technology.

Role type

Undergraduate co-op/intern ASIC Package Engineer

Builds

Substrate, interposer, and bump designs for AMD products, test vehicles, and probe card substrates

Domain

Semiconductor manufacturing / Advanced packaging

Required skills

Substrate design, Interposer design, Bump design, Design verification, Yield analysis, Defect metric analysis, Packaging material evaluation, Benchmarking, Perl scripting, Python scripting, SQL, PowerBI

Preferred skills

Transmission lines and electric circuits, Package/silicon/PCB design software, Semiconductor theory, Packaging process/technology

Technologies

Perl, Python, SQL, PowerBI, Package design software, Silicon design software, PCB design software

Responsibilities

Support package design and development engineers in project prioritization and optimization, Complete substrate, interposer, and bump designs, Implement design verification to ensure performance and quality, Analyze yield and defect metrics to improve design performance, Evaluate and benchmark packaging materials for cost-efficiency and performance