Summer 2027 Long Term ASIC Verification Engineering Intern/ Co-Op
Core
Developing advanced verification environments and IP components for ASIC and Adaptive SoC targeting next-gen communication networks and data centers.
Role type
ASIC Verification Engineering Intern
Builds
Configurable silicon for wired communication applications
Domain
Semiconductor / Hardware Verification
Required skills
SystemVerilog, UVM, C/C++, Digital Design, Object-Oriented Programming, Constrained Random Stimulus, Coverage-Driven Verification
Preferred skills
Python, Perl, AI tools
Technologies
SystemVerilog, UVM, Constrained Random Stimulus
Responsibilities
Develop SystemVerilog-UVM verification environments and IP components; Write tests, sequences, and testbench components; Employ Coverage-Driven Verification methodology; Review verification plans and design specifications; Automate tasks and evaluate new tools; Investigate and root cause issues in IP development.
Seniority
Intern
