FPGA/RTL Design Engineering Manager with High-Speed Protocols (HSIO) (PCIE/Ethernet/USB)
Core
Lead a Silicon Engineering group to manage FPGA/RTL design teams and deliver next-generation computing technologies using high-speed protocols.
Role type
Manager, Silicon Design Engineering (FPGA/RTL/HSIO)
Builds
Next-generation computing technologies (processors, AI systems)
Domain
Semiconductor / High-Speed Protocols (PCIe, Ethernet, USB)
Required skills
Team leadership, FPGA Verilog design, AMD/Xilinx tools, High-speed protocol design (Ethernet/PCIe/USB), System engineering, Mentoring, Problem-solving
Preferred skills
Distributed team management, Executive communication, Design of experiments
Technologies
Verilog, AMD/Xilinx, PCIe, Ethernet, USB
Responsibilities
Lead a high-performance engineering team, Form and nurture talent, Meet schedule commitments, Collaborate with multi-functional leaders
Seniority
Manager, hands-on technical leadership
