Senior ASIC Design Engineer - Memory Subsystem
Core
Designing micro-architecture and RTL for NVIDIA's Memory Subsystem, including SOC interconnects, ordering controllers, and memory accelerators.
Role type
Senior ASIC Design Engineer (Memory Subsystem)
Builds
High-performance GPU memory subsystems and interconnects for AI computing, robots, and autonomous vehicles.
Domain
Semiconductor / Hardware Design / Memory Subsystems
Deliverable
production ML models
Required skills
RTL design, synthesis, timing analysis, Verilog, VHDL, scripting (Perl), high-speed coherent interconnects, protocol bridges, hardware-managed coherency, system level caches, multiple clock domains, asynchronous interfaces, industry specifications (CHI/CXL/PCI-E)
Preferred skills
Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency, system level caches, multiple clock domains, asynchronous interfaces, industry specifications (CHI/CXL/PCI-E)
Technologies
Verilog, VHDL, Perl, CAD tools
Responsibilities
Collaborate with architects, verification, and physical design teams to deliver world-class solutions; responsible for micro-architecture and design including RTL design, synthesis, and timing analysis using innovative CAD tools and latest process technologies.
Seniority
Senior, hands-on IC
