Senior Full-Chip RTL Integration Engineer
Core
Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration.
Role type
Senior IC RTL Integration Engineer (SoC/ASIC)
Builds
Large-scale System-on-Chip (SoC) and ASIC designs
Domain
Semiconductor / Digital IC Design
Required skills
RTL Integration, SystemVerilog, UVM, DFT methodologies (Scan, ATPG, MBIST, LBIST, JTAG), Digital Design Fundamentals, SoC Architecture, Clocking & Reset, Bus Protocols, Lint/CDC/RDC, Design Signoff, Python/Perl/Tcl/Shell Scripting
Preferred skills
Large-scale SoC integration, High-speed interfaces, Processor subsystems, Memory controllers, Synopsys/Cadence/Siemens tools, Low-power design (UPF), AI-assisted development tools
Technologies
SystemVerilog, UVM, Python, Perl, Tcl, Shell, Synopsys, Cadence, Siemens, UPF
Responsibilities
Lead RTL integration of multiple IPs into complex ASIC/SoC designs; Drive system-level integration with Architecture, Verification, and Physical Design teams; Perform RTL quality checks including lint, CDC, RDC, and synthesis; Develop and execute integration-level verification plans; Collaborate with DFT teams to integrate test structures and review fault coverage; Support design signoff activities; Develop automation and scripting solutions for productivity.
Seniority
Senior, hands-on IC
