Senior ASIC Timing Engineer
Core
Lead timing analysis and closure for NVIDIA GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
Role type
Senior ASIC Timing Engineer
Builds
High-performance GPUs, CPUs, LPUs, and SoCs for AI computing, gaming, and accelerated computing
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), timing constraints generation, ECO implementation, crosstalk and noise analysis, physical design optimization, deep sub-micron process modeling
Preferred skills
GPU/CPUs/LPU/SOC domain experience, logic synthesis, equivalence checking, DFT timing closure, AMS design timing, flow development and automation
Technologies
Industry standard STA and timing convergence tools
Responsibilities
Drive timing analysis and closure processes; Collaborate with RTL, DFX, and Clocks teams to devise timing strategies; Improve timing convergence flows and methodology
Seniority
Senior, hands-on IC
