ASIC Design Engineer – Clocks IP
Core
Architecting clock domains and designing clocking topologies for GPU and CPU chips to satisfy functional, physical, and testing requirements.
Role type
ASIC Design Engineer (Clocks IP)
Builds
GPU and CPU chips with optimized clocking networks
Domain
Semiconductor / ASIC Design / GPU & CPU
Required skills
RTL design (Verilog), logic synthesis, Python scripting, logic optimization, PPA trade-offs, timing closure, sub-micron silicon issues (noise, cross-talk, OCV)
Preferred skills
On-chip clocking networks, clocks controller design, system-level artifacts (power, noise), scalable architecture, hands-on silicon debug
Technologies
Verilog, Python
Responsibilities
Architect clock domains to satisfy design requirements; Engage with multiple teams to design clocks satisfying architectural constraints; Improve PPA by evaluating trade-offs and implementing new clocking topologies; Collaborate with physical design and timing teams for high-speed clocking solutions; Deliver clock RTL information to verification and timing teams; Participate in end-to-end ASIC execution from micro-arch to silicon bringup
Seniority
Mid-level (2+ years experience)
