ASIC Physical Design Intern - 2027
Core
Intern role focused on ASIC physical design tasks from RTL frozen to tape out, including synthesis, verification, and timing closure.
Role type
ASIC Physical Design Intern
Builds
Digital chips for high-frequency, low-power applications
Domain
Semiconductor / IC Design
Required skills
IC design knowledge, RTL/netlist quality check, formal verification, constraints creation, timing analysis, Python/TCL scripting
Preferred skills
IC backend implementation experience, EDA tools (Synopsys DC/PT/Formality, Cadence RC/LEC), flow automation development
Technologies
Synopsys DC, Synopsys PT, Synopsys Formality, Cadence RC Compiler, Cadence LEC, Python, TCL
Responsibilities
Chip integration and netlist generation, Synthesis and RTL/netlist quality check, Constraints creation and timing closure, Collaboration with PR engineers for chip implementation, Develop and improve timing closure flow from frontend to backend
Seniority
Intern
