ASIC Physical Design Engineer (RDSS Intern)
Core
ASIC Physical Design Engineer (RDSS Intern) responsible for chip implementation from RTL frozen to tape out, including synthesis, formal verification, timing closure, and flow automation.
Role type
ASIC Physical Design Engineer (Research and Development Substitute Services Intern)
Builds
High-performance digital chips for AI, GPUs, and accelerated computing
Domain
Semiconductor / VLSI Design
Deliverable
production ML models
Required skills
RTL design, Synthesis, Formal Verification, Timing Closure, Constraints definition, Floorplanning, Netlist generation, EDA tools (Synopsys/Cadence), Python/TCL scripting
Preferred skills
Advanced process node knowledge, Flow automation development, Methodology development
Responsibilities
Chip integration and netlist generation, Synthesis, RTL/netlist quality check, Formal Verification, Constraints creation and validation, Analyze/resolve special timing issues, Cross-team collaboration for chip partitioning and floorplan, Achieve timing closure for partition and full chip level, Function eco creation, Develop and improve timing closure flow, Flow automation development
Seniority
Intern
