Senior VLSI Engineer
Core
Physical design of high-speed communication chips, optimizing power, area, and performance while resolving timing and congestion issues.
Role type
Senior IC physical design engineer (networking silicon)
Builds
High-throughput, low-latency networking chips
Domain
Semiconductor / Networking
Required skills
RTL2GDS flows, PNR, STA, physical verification, LVS/DRC, EDA tools (Synopsys, Cadence), power/clock distribution, place and route, timing closure, noise analysis
Preferred skills
High cell count design experience, HS blocks experience, inflows development experience
Technologies
Synopsys, Cadence
Responsibilities
Perform physical design of blocks under challenging constraints; Resolve complex timing and congestion problems; Execute RTL2GDS flows including synthesis, place and route, and verification; Participate in inflows development
Seniority
Senior, hands-on IC
