CareerPlan

Senior Packaging Technical Engineer - Hardware

US, CA, Santa ClaraFull-time$168k–$259k2026-08-18 → 2026-11-10

Core

Define and implement silicon pad rings, substrate interconnect schemes, and lead package layout design for advanced GPU packages.

Role type

Senior IC packaging technical engineer (hardware)

Builds

Robust, world-class electrical packages for GPUs

Domain

Semiconductor / Hardware / Packaging

Required skills

Chip pad ring definition, substrate interconnect design, package layout design, chip floor planning, transmission line theory, power delivery, signal integrity

Preferred skills

Board/system design, Perl/Python/Tcl scripting, Cadence Skill, Excel

Technologies

Cadence Skill, Perl, Python, Tcl, Excel

Responsibilities

Define and implement chip pad rings, define substrate interconnect schemes, lead package layout design process, work with large cross-functional teams (Circuit, Signal Integrity, RTL, Place and Route)

Seniority

Senior, hands-on IC