Physical Design Engineer, Synthesis and Implementation
Core
Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions to deliver high-speed communication devices with highest throughput and lowest latency.
Role type
Senior IC physical design engineer (synthesis and implementation)
Builds
High-speed networking silicon chips (GPUs/AI accelerators)
Domain
Semiconductor / Networking / Digital Logic
Required skills
RTL-to-gate synthesis, QoR optimization, place-and-route flow, timing analysis, Python, Perl, Tcl, Make
Technologies
Synopsys Fusion Compiler, Cadence Genus
Responsibilities
Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets; Analyze design bottlenecks and QoR regressions collaborating with RTL, timing, architecture, and physical design teams; Support physical implementation from floorplanning and power planning through routing and timing closure; Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies.
Seniority
Mid-level, hands-on IC
