Senior Memory Post Silicon Qualification Engineer
Core
Own high-speed memory bring-up, characterization, and qualification on flagship GPU, CPU, and SoC programs, root-causing marginality issues before software hardening.
Role type
Senior IC memory qualification engineer (post-silicon)
Builds
High-speed memory interfaces (GDDR, LPDDR, HBM) and qualification playbooks for GPUs, CPUs, and SoCs
Domain
Semiconductor hardware, high-performance computing, memory subsystems
Deliverable
production ML models
Required skills
GDDR/LPDDR/HBM protocol and physical-layer expertise, root-cause analysis of memory failures, hands-on lab instrumentation (oscilloscope, protocol analyzers), PCB stack-up and SI/PI knowledge, AI-driven workflow design for margin analysis
Preferred skills
Experience codifying reusable qualification methodologies, building agentic AI workflows for debug assistance, cross-boundary failure resolution across silicon/firmware/board
Technologies
GDDR, LPDDR, HBM, shmoo analysis, margin analysis, AI/ML for debug, protocol analyzers, thermal chambers
Responsibilities
Bring up high-speed memory interfaces from first power-on through full PVT characterization; Lead root-cause closure on multi-team memory failures spanning silicon, controller, PHY, and board; Design and deploy AI-enabled workflows for margin data analysis and failure signature detection; Partner with pre-Si architecture and DV teams to translate features into validation plans
Seniority
Senior, hands-on IC
