Senior ASIC Verification Engineer - PMU
Core
Architect and implement the micro-architecture for the next generation Power Management Unit (PMU) IP, which includes a RISC-V core and custom control logic, to optimize chip performance and efficiency for AI datacenter applications.
Role type
Senior IC ASIC verification engineer (PMU)
Builds
PMU IP for AI datacenter chips
Domain
Semiconductor / Power Management / RISC-V
Required skills
RTL design, frontend ASIC design, micro-architecture definition, silicon debug, RISC-V core knowledge, power feature implementation
Preferred skills
active power/low power design experience, system-level control features experience
Technologies
RISC-V, RTL, ASIC
Responsibilities
Collaborate with production SW and power architecture teams to define architecture/micro-architecture for power features; Support silicon debug by understanding PMU function impact on the system; Implement micro-architecture to RTL design.
