HSIO Validation Lead – Silicon Co-Design
Core
Own post-silicon bring-up, characterization, validation, and debug of high-speed interfaces (PCIe, NVLink, C2C) across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness.
Role type
Senior IC HSIO Validation Lead (Silicon Co-Design)
Builds
High-speed interface validation strategies, automated debug AI agents, and robust interoperability across complex multi-device system topologies.
Domain
Semiconductor / High-Speed Interface / Silicon Validation
Deliverable
production ML models
Required skills
HSIO bring-up and validation, PCIe/NVLink/CXL/C2C protocol expertise, signal integrity fundamentals (SERDES, link training, equalization), hands-on lab tool proficiency (oscilloscopes, BERTs, protocol analyzers), full-stack debugging (hardware/firmware/drivers), statistical analysis of marginal distributions
Preferred skills
Advanced SERDES validation, AI-driven debug flow deployment, solving customer-critical failures under pressure, technical direction of validation organizations
Technologies
PCIe, NVLink, CXL, C2C, Ethernet, USB, SERDES, oscilloscopes, BERTs, protocol analyzers, logic analyzers
Responsibilities
Define validation strategy and test coverage, close hardest failures by driving root cause across protocol and silicon, own and build AI agents for automated debug triage, ensure robust interoperability across ecosystem components, sit at decision tables to align cross-functional teams, translate real silicon learnings into methodology improvements
Seniority
Senior, hands-on IC
