Memory Mask Design Engineer
Core
Designing high-speed digital memory circuits and implementing IC layouts for advanced CMOS process nodes.
Role type
Senior IC memory layout engineer
Builds
Full Custom Memory group digital memory circuits and IP layouts
Domain
Semiconductor / Advanced CMOS process nodes (3nm, 5nm, 7nm)
Required skills
IC layout implementation, advanced CMOS process knowledge, EDA tools (Cadence), high-performance memory layout, bitcell design, decoder design, LIO design, floor planning, block level routing, macro level assembly, top level verification, EM/IR quality checks, layout dependent effects (LOD, Dummification, fills)
Preferred skills
null
Technologies
Cadence, 3nm, 5nm, 7nm
Responsibilities
Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies. Deliver layouts for Full Custom Memory group specializing in digital Memory circuits. Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts. Follow company procedures and practices for IC layout activities.
Seniority
Mid-level, hands-on IC
