Senior Manager, DPU Performance and System Validation
Core
Lead a team of 25+ engineers to define Performance Verification plans, coordinate performance emulation and system validation, and manage post-silicon debugging for DPU chips.
Role type
Senior Manager, DPU Performance and System Validation
Builds
DPU chips (Data Processing Units)
Domain
Semiconductor / ASIC Development
Deliverable
production ML models
Required skills
Performance management in chip build, Team leadership (25+ engineers), DPU performance expertise, System validation, Performance emulation, Post-silicon debugging, Cross-functional collaboration
Preferred skills
None stated
Technologies
None stated
Responsibilities
Lead and manage a group of 25+ engineers; Collaborate with the ARCH team to define and implement the Performance Verification (PV) Plan; Coordinate the performance emulation and functional validation processes; Participate in post-silicon performance debugging; Develop and unify performance debug processes across all platforms
Seniority
Senior, hands-on IC
