Senior Cell Modeling and Verification Engineer
Core
Develop behavioral models and verification for custom mixed-signal design cells used across NVIDIA products.
Role type
Senior IC hardware verification engineer (mixed-signal/ASIC)
Builds
Verified RTL and high-performance design cells for SoCs and GPUs
Domain
Semiconductor / ASIC design
Required skills
Verilog HDL, SystemVerilog, RTL simulation, waveform debug, Python scripting, Perl scripting, digital design concepts, logic design
Preferred skills
Mixed-signal design experience, PLL knowledge, high-speed interconnects
Technologies
Verilog, SystemVerilog, Perl, Python
Responsibilities
Develop behavioral models and verification for custom mixed-signal design cells; Model, verify, and emulate/prototype mixed-signal designs using Verilog/SystemVerilog; Collaborate on library build, cell integration, ASIC verification, and DFT simulation; Document and deliver fully verified RTL to achieve design targets.
Seniority
Senior, hands-on IC
