Senior Signal and Power Integrity Engineer
Core
Design high-frequency channels up to 400Gb/s per lane for PCBs, packages, connectors, and cables, and develop layout guidelines for systems.
Role type
Senior IC signal and power integrity engineer
Builds
PHY ICs and high-speed interface systems
Domain
Semiconductors / High-speed digital design
Required skills
Electromagnetics and transmission line theory, EM simulation tools (Ansys EM, CST), high-speed I/O design (clock generation, transmitter/receiver, equalization), lab measurements (VNA, TDR), InfiniBand/Ethernet/PCI-Ex Layer 1 specifications
Preferred skills
PDN analysis and time domain simulation, NRZ/PAM-4 signaling schemes, co-simulation of circuits and PDN models, MATLAB/Python/C programming, TSV modeling
Technologies
Ansys EM, CST, VNA, TDR, Network Analyzer, InfiniBand, Ethernet, PCI-Ex
Responsibilities
Design high-frequency channels for PCBs, packages, connectors, and cables; Simulate passive and active elements in 3D and 2D tools; Measure systems in the lab using Network Analyzer, TDR, and scope; Master InfiniBand, Ethernet, and PCI-Ex Layer 1 specifications and implementation methods
Seniority
Senior, hands-on IC
