Senior Physical Design Backend Engineer
Core
Physical design of high-speed communication blocks for networking chips, optimizing power, area, and performance under challenging constraints.
Role type
Senior Physical Design Backend Engineer
Builds
High-speed networking silicon chips
Domain
Semiconductor / Networking
Required skills
RTL2GDS flows, Place and Route (PNR), Static Timing Analysis (STA), Physical Verification (LVS/DRC), Power and Clock Distribution, Congestion Resolution, EDA tool expertise
Preferred skills
High cell count design experience, Flow development
Technologies
Synopsys, Cadence
Responsibilities
Perform physical design of blocks targeting best power, area, and performance; Resolve complex timing and congestion problems; Execute RTL2GDS flows including synthesis, place and route, and timing closure; Participate in flow development.
Seniority
Senior, hands-on IC
