Senior Design-for-Test Engineer, ATPG
Core
Senior DFT Engineer responsible for ATPG flows, architecture, and post-silicon validation for advanced semiconductor chips.
Role type
Senior IC design-for-test engineer (ATPG)
Builds
Next-generation DFT technologies and production test flows for NVIDIA chips
Domain
Semiconductor / Hardware Design
Required skills
ATPG tools, DFT ASIC design, automation flow development, pattern generation, fault simulation, post-silicon bring-up, scripting (TCL, Python, Unix shell)
Preferred skills
Mentor TestKompress ATPG tool, retargeting flow, ATE experience, on-chip scan compression, BIST
Technologies
ATPG, Scan, BIST, TestKompress, ATE, TCL, Python, Unix shell
Responsibilities
Lead state-of-the-art DFT/ATPG flows and implementation; Own ATPG projects from architecture to post-silicon diagnosis; Invent and maintain automation flows for short test time
Seniority
Senior, hands-on IC
