Senior IP DV Engineer - NOC IP
Core
Verify ASIC design, architecture, and micro-architecture of memory sub-systems/units for next-generation GPUs and SOCs.
Role type
Senior IC verification engineer (memory subsystems)
Builds
Memory subsystems for GPUs and SOCs
Domain
Semiconductor / Hardware Verification
Required skills
ASIC verification, random stimulus generation, functional coverage, assertion-based verification, Verilog, SystemVerilog, UVM, VMM, bus functional modeling, scoreboards
Preferred skills
Memory subsystem IP verification, network interconnect IP verification, debugging, scripting
Technologies
Verilog, SystemVerilog, UVM, VMM
Responsibilities
Define verification scope and develop verification infrastructure, create test plans and tests for complex IPs, build reusable bus functional models and scoreboards, perform functional coverage closure, collaborate with architects and silicon verification teams
Seniority
Senior, hands-on IC
