Senior SRAM Circuit Design Engineer
Core
Designing embedded SRAM macros and developing automated SRAM compilers for NVIDIA's SOC design partners.
Role type
Senior IC SRAM circuit design engineer
Builds
SRAM macros and automated SRAM compilers for high-performance GPUs and AI chips
Domain
Semiconductor / Digital Integrated Circuit Design
Deliverable
production ML models
Required skills
Transistor-level circuit design, SRAM macro design (single/dual-port, register files), layout implementation, physical and logical verification, debug, Python scripting, FinFET process knowledge
Preferred skills
MSEE or PhD, Cadence schematic and layout capture tools, silicon testing/debug experience, advanced Python scripting expertise
Technologies
Python, Cadence
Responsibilities
Design transistor-level SRAM circuits, supervise layout implementation, perform physical and logical verification, debug SRAM macros, develop efficient SRAM compilers, collaborate with SOC design teams to meet performance and cost goals
Seniority
Senior, hands-on IC
