Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis)
Core
Develop, optimize, and implement the full wafer-to-die preparation flow including thinning, dicing, cleaning, laser marking, and package singulation to support high-quality die for downstream assembly.
Role type
Senior IC process engineer (semiconductor wafer/die preparation)
Builds
Wafer-to-die preparation flow and high-quality die for flip-chip, wire-bond, and other assembly flows
Domain
Semiconductor manufacturing / RF filters / Wafer processing
Required skills
Wafer back-grinding and thinning, mechanical wafer dicing, die cleaning and handling, laser marking, package singulation, DOE design, statistical process control, equipment qualification, defect troubleshooting
Preferred skills
SiC and hard materials processing, thin-film wafer handling, machine-vision/OCR verification, CAD (AutoCAD/SolidWorks), OSAT/external partner support, JEDEC/SEMI/IPC standards
Technologies
JMP, Minitab, MATLAB, Python, AutoCAD, SolidWorks
Responsibilities
Develop and qualify wafer back-grinding, thinning, stress-relief, and backside finishing processes; optimize mechanical wafer dicing parameters and blade selection; establish post-dice die cleaning, drying, and handling methods; develop and qualify laser marking processes; run DOEs, define process windows, troubleshoot defects, and transfer robust processes into manufacturing
Seniority
Mid-level, hands-on IC