Senior/Staff Process Engineer (Wafer Dicing & Back-grind)
Core
Develop and optimize silicon photonic wafer backside grinding/thinning, laser stealth dicing, and die sorting processes to ensure chip quality and yield.
Role type
Senior/Staff Process Engineer (Silicon Photonic Manufacturing)
Builds
Silicon photonic chips via OSAT or internal lines
Domain
Semiconductor manufacturing / Silicon Photonics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Wafer thinning/grinding optimization, Laser stealth dicing, Die sorting, Process abnormality resolution (warpage, cracking, chipping), Process integration with bumping/flip-chip, SOP/WI documentation, NPI support, SPC, JMP data analysis, DOE matrix design
Preferred skills
Experience with advanced packaging wafers, Supplier qualification for equipment/materials
Technologies
SPC, JMP
Responsibilities
Optimize wafer thinning thickness, grinding speed, cutting path, and laser parameters; Solve process abnormalities like wafer warpage and chip breakage; Monitor thickness uniformity and production capacity; Evaluate process compatibility with subsequent packaging steps; Compile process documentation and support new product introduction.
Seniority
Senior, hands-on IC
