PD Architect
Core
Lead physical design implementation and convergence activities for high-performance SOCs/ASICs from RTL to GDSII, ensuring timing closure, power optimization, and signoff for products in AI, gaming, and automotive domains.
Role type
Senior IC Physical Design Architect
Builds
High-performance SOCs/ASICs for AI Data Centres, Game Consoles, High-end Discrete Graphics, and Automotive applications
Domain
Semiconductor / Physical Design
Required skills
RTL2GDSII implementation, Timing closure, Power optimization, Physical verification, IP integration, Cross-functional leadership, Methodology development, Scripting (Perl/TCL/Python), EDA tool expertise
Preferred skills
15+ years in Physical Design, SOC/Block-level implementation, PPA optimization, AI technologies integration, Foundry DRM collaboration
Technologies
Synopsys Fusion Compiler, ICC2, Primetime, Redhawk, PTPX, VCLP, Formal Equivalence, Low Power Checks
Responsibilities
Drive physical design implementation and signoff strategies for multiple SOC/ASICs; Provide leadership and mentoring for complex tile/partition convergence; Collaborate with architecture, verification, and product teams to meet PPA goals; Define and track KPIs for RTL2GDSII activities; Mentor team members and communicate technical concepts to stakeholders; Stay abreast of industry advancements and represent the company in forums.
Seniority
Senior, hands-on IC with strategic leadership
