Lead RTL design Engineer
Core
Lead RTL design and integration of System-on-Chip (SoC) logic, IP, and power domains for AMD's high-performance computing and AI processors.
Role type
Senior IC RTL Design Engineer (SoC)
Builds
Next-generation SoCs for supercomputing, high-performance computing, cloud, and AI
Domain
Semiconductor / Hardware Design
Required skills
Verilog RTL development, SoC integration, SoC architecture, AXI/PCIe protocols, UPF low-power methodologies, Static Timing Analysis (STA), Physical design interaction, Tcl/Perl/Ruby/Shell scripting, Formal verification
Preferred skills
Debugging simulation/integration issues, Top-level synthesis support, Leading design domains
Technologies
Verilog, UPF, Tcl, Perl, Ruby, Shell, AXI, PCIe
Responsibilities
SoC-level design and integration, RTL design and coding for SoC logic, SoC power design and implementation, Static verification (Lint, CDC, RDC, Power, Connectivity), Debugging simulation issues, Supporting top-level synthesis
Seniority
Senior, hands-on IC
